Intel Corp Splits Graphic Chips Unit Into Two To Evolve Its Business Structure – Tech Business News

Intel is splitting its graphic chips unit into two, the company said on Wednesday, as it realigns the business to better compete with Nvidia Corp, Advanced Micro Devices and to help it’s CPU, GPU and AI efforts.

The computer chip company says the consumer graphics department will be joined together with its client computing group, which creates chips for computers, and the accelerated computing teams will combine with its data centre and AI division.

The move comes as Intel doubles down on accelerated computing, a growing segment dominated by Nvidia as AI use surges.

Raja Koduri, who heads the Accelerated Computing Systems and Graphics unit, will move to back to his previous position as Intel chief architect.

Koduri, whose career includes spells at Apple and AMD, is being given oversight of Intel’s long-term technology programmes such as developing advanced memory and integrating different types of chips to achieve higher performance computing, says the publication, adding that he will work in cooperation with Intel’s design teams.

“Discrete graphics and accelerated computing are critical growth engines for Intel,” Intel says in a statement. “We are evolving our structure to accelerate and scale their impact and drive go-to-market strategies with a unified voice to customers.” said Koduri.

Koduri has previous experience at Apple and AMD, working as the senior VP and chief architect for AMD’s Radeon technologies before joining Intel in 2017.

Intel has faced a continuing decrease in worldwide personal computer sales, which resulted in a 20% decrease in their revenues to $15.3 billion in the past quarter and also gave downbeat predictions for their profits and income throughout the rest of the year.

Despite various difficulties, Intel has ambitious objectives for their chip-making industry. During the Hot Chips event of the semiconductor sector in August, CEO Pat Gelsinger said that the firm aims to increase the number of transistors on a package from the present 100 billion to one trillion by the year 2030.